View ALD1726ESAL_4874537.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev 2.1 ?2011 advanced linear devices, inc. 415 tasman drive, sunnyvale, ca 94089-1706 tel: (408) 747-1155 fax: (408) 747-1286 www.aldinc.com general description the ald1726e is a monolithic rail-to-rail ultra-micropower precision cmos operational amplifier with integrated user programmable epad (electrically programmable analog device) based offset voltage adjust- ment. the ald1726e is a direct replacement of the ald1706 operational amplifier, with the added feature of user-programmable offset voltage trimming resulting in significantly enhanced total system performance and user flexibility. epad technology is an exclusive ald design which has been refined for analog applications where precision voltage trimming is necessary to achieve a desired performance. it utilizes cmos fets as in- circuit elements for trimming of offset voltage bias characteristics with the aid of a personal computer under software control. once programmed, the set parameters are stored indefinitely within the device even after power- down. epad offers the circuit designer a convenient and cost-effective trimming solution for achieving the very highest amplifier/system perfor- mance. the ald1726e operational amplifier features rail-to-rail input and output voltage ranges, tolerance to over-voltage input spikes of 300mv beyond supply rails, extremely low input currents of 0.01pa typical, high open loop voltage gain, useful bandwidth of 200khz, slew rate of 0.17v/ m s, and low typical supply current of 25 m a. benefits ? eliminates manual and elaborate system trimming procedures ? remote controlled automated trimming ? in-system programming capability ? no external components ? no internal chopper clocking noise ? no chopper dynamic power dissipation ? simple and cost effective ? small package size ? extremely small total functional volume size ? low system implementation cost ? micropower and low voltage applications ? sensor interface circuits ? transducer biasing circuits ? capacitive and charge integration circuits ? biochemical probe interface ? signal conditioning ? portable instruments ? high source impedance electrode amplifiers ? precision sample and hold amplifiers ? precision current to voltage converter ? error correction circuits ? sensor compensation circuits ? precision gain amplifiers ? periodic in-system calibration ? system output level shifter key features ? epad (electrically programmable analog device) ? user programmable v os trimmer ? computer-assisted trimming ? rail-to-rail input/output ? compatible with standard epad programmer ? high precision through in-system circuit precision trimming ? reduces or eliminates v os , psrr, cmrr and tcv os errors ? system level calibration capability ? application-specific programming mode ? in-system programming mode ? electrically programmable to compensate for external component tolerances ? achieves 0.01pa input bias current and 50 m v input offset voltage simultaneously ? compatible with industry standard pinout ordering information (l suffix denotes lead-free (rohs)) operating temperature range 0 c to +70 c0 c to +70 c -55 c to +125 c 8-pin 8-pin 8-pin small outline plastic dip cerdip package (soic) package package ALD1726ESAL ald1726epal ald1726eda * contact factory for leaded (non-rohs) or high temperature versions. pin configuration 1 2 2 3 4 8 7 6 5 ve1 -in +in ve2 out n/c v - v + top view sal, pal, da packages * n/c pin is internally connected. do not connect externally. e epad tm ? n a b l e d e epad ? ultra micropower cmos operational amplifier ald1726e a dvanced l inear d evices, i nc.
ald1726e advanced linear devices 2 of 13 functional description the ald1726e uses epads as in-circuit elements for trim- ming of offset voltage bias characteristics. each ald1726e has a pair of epad-based circuits connected such that one circuit is used to adjust v os in one direction and the other circuit is used to adjust v os in the other direction. while each of the epad devices is a monotonically adjustable program- mable device, the v os of the ald1726e can be adjusted many times in both directions. once programmed, the set v os levels are stored permanently, even when the device power is removed. the ald1726e is pre-programmed at the factory under standard operating conditions for minimum equivalent input offset voltage. it also has a guaranteed offset voltage pro- gram range, which is ideal for applications that require electrical offset voltage programming. the ald1726e is an operational amplifier that can be trimmed with user application-specific programming or in- system programming conditions. user application-specific circuit programming refers to the situation where the total input offset voltage of the ald1726e can be trimmed with the actual intended operating conditions. for example, an application circuit may have +6v and -2.5v power supplies, and the operational amplifier input is biased at +0.7v, and an average operating temperature at 55 c. the circuit can be wired up to these conditions within an environmental chamber with ald1726e inserted into a test socket connected to this circuit while it is being electrically trimmed. any error in v os due to these bias conditions can be automatically zeroed out. the total v os error is now limited only by the adjustable range and the stability of v os , and the input noise voltage of the operational amplifier. therefore, this total v os error now includes v os as v os is traditionally specified; plus the v os error contributions from psrr, cmrr, tcv os , and noise. typically this total v os error term (v ost ) is approximately 50 m v for the ald1726e. the v os contribution due to psrr, cmrr, tcv os and external components can be large for operational amplifiers without trimming. therefore the ald1726e with epad trimming is able to provide much improved system perfor- mance by reducing these other sources of error to provide significantly reduced v ost. in-system programming refers to the condition where the epad adjustment is made after the ald1726e has been inserted into a circuit board. in this case, the circuit design must provide for the ald1726e to operate in normal mode and in programming mode. one of the benefits of in-system programming is that not only is the ald1726e offset voltage from operating bias conditions accounted for, any residual errors introduced by other circuit components, such as resistor or sensor induced voltage errors, can also be cor- rected. in this way, the in-system circuit output can be adjusted to a desired level, eliminating the need for another trimming function. user programmable v os feature each ald1726e has two pins named ve1 and ve2 which are internally connected to an internal offset bias circuit. ve1/ ve2 have initial typical values of 1.0v to 1.5v. the voltage on these pins can be programmed using the ald e100 epad programmer and the appropriate adapter module. the useful programming range of ve1 and ve2 is 1.2v to 3.0v. ve1 and ve2 pins are programming pins, used during programming mode to inject charge into the internal epads. increasing voltage on ve1 decreases the offset voltage whereas increasing voltage on ve2 increases the offset voltage of the operational amplifier. the injected charge is permanently stored and determines the offset voltage of the operational amplifier. after programming, ve1 and ve2 terminals must be left open to settle on a voltage determined by internal bias currents. during programming, the voltages on ve1 or ve2 are in- creased incrementally to set the offset voltage of the opera- tional amplifier to the desired vos. note that desired vos can be any value within the offset voltage programmable ranges, and can be zero, a positive value or a negative value. this v os value can also be reprogrammed to a different value at a later time, provided that the useful ve1 or ve2 program- ming voltage range has not been exceeded. ve1 or ve2 pins can also serve as capacitively coupled input pins. internally, ve1 and ve2 are programmed and connected differentially. temperature drift effects between the two internal offset bias circuits cancel each other and introduce less net temperature drift coefficient change than offset voltage trimming techniques such as offset adjustment with an external trimmer potentiometer. while programming, v+, ve1 and ve2 pins may be alter- nately pulsed with 12v (approximately) pulses generated by the epad programmer. in-system programming requires the ald1726e application circuit to accommodate these programming pulses. this can be accomplished by adding resistors at certain appropriate circuit nodes. for more information, see application note an1700.
ald1726e advanced linear devices 3 of 13 supply voltage, v + 10.6v differential input voltage range -0.3v to v + +0.3v power dissipation 600 mw operating temperature range sal,pal packages 0 c to +70 c da package -55 c to +125 c storage temperature range -65 c to +150 c lead temperature, 10 seconds +260 c caution: esd sensitive device. use static control procedures in esd controlled environment. absolute maximum ratings operating electrical characteristics t a = 25 o c v s = 2.5v unless otherwise specified ald1726e parameter symbol min typ max unit test conditions supply voltage v s 1.0 5.0 v v + 2.0 10.0 v single supply initial input offset voltage 1 v os i 50 100 m vr s 100k w offset voltage program range 2 d v os 10 20 mv programmed input offset v os 50 100 m v at user specified voltage error 3 target offset voltage total input offset voltage 4 v ost 50 100 m v at user specified target offset voltage input offset current 5 i os 0.01 10 pa t a = 25 c 240 pa 0 c t a +70 c input bias current 5 i b 0.01 10 pa t a = 25 c input voltage range 6 v ir -0.3 5.3 v v + = +5v -2.8 +2.8 v v s = 2.5v input resistance r in 10 14 w input offset voltage drift 7 tcv os 7 m v/ cr s 100k w initial power supply psrr i 80 db r s 100k w rejection ratio 8 initial common mode cmrr i 83 db r s 100k w rejection ratio 8 large signal voltage gain a v 32 100 v/mv r l =1m w 20 v/mv 0 c t a +70 c v o low 0.001 0.01 v r l =1m w v + = 5v output voltage range v o high 4.99 4.999 v 0 c t a +70 c v o low -2.48 -2.40 v r l =100k w v o high 2.40 2.48 v 0 c t a +70 c output short circuit current i sc 200 m a * notes 1 through 9, see "definitions and design notes" on page 6.
ald1726e advanced linear devices 4 of 13 t a = 25 o c v s = 2.5v unless otherwise specified 1726e parameter symbol min typ max unit test conditions average long term input offset d v os 0.02 m v/ voltage stability 9 d time 1000 hrs initial ve voltage ve1 i , ve2 i 1.0 v programmable ve range d ve1, d ve2 1.0 2.0 v programmed ve voltage error e(ve1-ve2) 0.1 % ve pin leakage current i eb -5 m a operating electrical characteristics (cont'd) t a = 25 o c v s = 2.5v unless otherwise specified 1726e parameter symbol min typ max unit test conditions supply current i s 25 40 m av in = 0v no load power dissipation p d 200 m wv s = 2.5v input capacitance c in 1 pf maximum load capacitance c l 25 pf equivalent input noise voltage e n 55 nv/ ? hz f = 1khz equivalent input current noise i n 0.6 fa/ ? hz f =10hz bandwidth b w 400 khz slew rate s r 0.17 v/ m sa v = +1 r l = 1m w rise time t r 1.0 m sr l = 1m w overshoot factor 20 % r l = 1m w , c l = 25pf settling time t s 10 m s 0.1% a v = 1,r l =1m w c l = 25pf
ald1726e advanced linear devices 5 of 13 operating electrical characteristics (cont'd) v s = 2.5v -55 c t a +125 c unless otherwise specified 1726e parameter symbol min typ max unit test conditions initial input offset voltage v os i 0.7 mv r s 100k w input offset current i os 2.0 na input bias current i b 2.0 na initial power supply psrr i 75 db r s 1m w rejection ratio 8 initial common mode cmrr i 83 db r s 1m w rejection ratio 8 large signal voltage gain a v 15 50 v/mv r l = 1m w output voltage range v o low -2.40 -2.30 v v o high 2.30 2.40 v r l = 1m w t a = 25 o c v s = 1.0v unless otherwise specified 1726e parameter symbol min typ max unit test conditions initial power supply psrr i 70 db r s 1m w rejection ratio 8 initial common mode cmrr i 70 db r s 1m w rejection ratio 8 large signal voltage gain a v 50 v/mv r l = 1m w output voltage range v o low -0.95 -0.9 v r l = 1m w v o high 0.9 0.95 bandwidth b w 0.3 mhz slew rate s r 0.17 v/ m sa v = +1, c l = 50pf
ald1726e advanced linear devices 6 of 13 definitions and design notes: 1. initial input offset voltage is the initial offset voltage of the ald1726e operational amplifier when shipped from the factory. the device has been pre-programmed and tested for program- mability. 2. offset voltage program range is the range of adjustment of user specified target offset voltage. this is typically an adjust- ment in either the positive or the negative direction of the input offset voltage from an initial input offset voltage. the input offset programming pins, ve1 or ve2, change the input offset voltage in the negative or positive direction, respectively. user specified target offset voltage can be any offset voltage within this pro- gramming range. 3. programmed input offset voltage error is the final offset voltage error after programming when the input offset voltage is at target offset voltage. this parameter is sample tested. 4. total input offset voltage is the same as programmed input offset voltage, corrected for system offset voltage error. usu- ally this is an all inclusive system offset voltage, which also includes offset voltage contributions from input offset voltage, psrr, cmrr, tcv os and noise. it can also include errors introduced by external components, at a system level. pro- grammed input offset voltage and total input offset voltage is not necessarily zero offset voltage, but an offset voltage set to compensate for other system errors as well. this parameter is sample tested. 5. the input offset and bias currents are essentially input protection diode reverse bias leakage currents. this low input bias current assures that the analog signal from the source will not be distorted by it. for applications where source impedance is very high, it may be necessary to limit noise and hum pickup through proper shielding. 6. input voltage range is determined by two parallel comple- mentary input stages that are summed internally, each stage having a separate input offset voltage. while total input offset voltage can be trimmed to a desired target value, it is essential to note that this trimming occurs at only one user selected input bias voltage. depending on the selected input bias voltage relative to the power supply voltages, offset voltage trimming may affect one or both input stages. for the ald1726e, the switching point between the two stages occurs at approximately 1.5v below the positive supply voltage. 7. input offset voltage drift is the average change in total input offset voltage as a function of ambient temperature. this parameter is sample tested. 8. initial psrr and initial cmrr specifications are provided as reference information. after programming, error contribution to the offset voltage from psrr and cmrr is set to zero under the specific power supply and common mode conditions, and be- comes part of the programmed input offset voltage error. 9. average long term input offset voltage stability is based on input offset voltage shift through operating life test at 125 c extrapolated to t a = 25 c, assuming activation energy of 1.0ev. this parameter is sample tested. additional design notes: a. the ald1726e is internally compensated for unity gain stability using a novel scheme which produces a single pole role off in the gain characteristics while providing more than 60 degrees of phase margin at unity gain frequency. a unity gain buffer using the ald1726e will typically drive 25pf of external load capacitance. b. the ald1726e has complementary p-channel and n-channel input differential stages connected in parallel to accomplish rail- to-rail input common mode voltage range. the switching point between the two differential stages is 1.5v below positive supply voltage. for applications such as inverting amplifiers or non- inverting amplifiers with a gain larger than 2.5 (5v operation), the common mode voltage does not make excursions below this switching point. however, this switching does take place if the operational amplifier is connected as a rail-to-rail unity gain buffer and the design must allow for input offset voltage varia- tions. c. the output stage consists of class ab complementary output drivers. the oscillation resistant feature, combined with the rail- to-rail input and output feature, makes the ald1726e an effec- tive analog signal buffer for high source impedance sensors, transducers, and other circuit networks. d. the ald1726e has static discharge protection. however, care must be exercised when handling the device to avoid strong static fields that may degrade a diode junction, causing in- creased input leakage currents. the user is advised to power up the circuit before, or simultaneously with, any input voltages applied and to limit input voltages not to exceed 0.3v of the power supply voltage levels. e. ve1 and ve2 are high impedance terminals, as the internal bias currents are set very low to a few microamperes to conserve power. for some applications, these terminals may need to be shielded from external noise coupling sources. for example, digital signals running nearby may cause unwanted offset volt- age fluctuations. care during the printed circuit board layout, to place ground traces around these pins and to isolate them from digital lines, will generally eliminate such coupling effects. in addition, optional decoupling capacitors of 1000pf or greater value can be added to ve1 and ve2 terminals. f. the ald1726e is designed for use in low voltage, micropower circuits. the maximum operating voltage during normal opera- tion should remain below 10v at all times. care should be taken to insure that the application in which the device is used does not experience any positive or negative transient voltages that will cause any of the terminal voltages to exceed this limit. g. all inputs or unused pins except ve1 and ve2 pins should be connected to a supply voltage such as ground so that they do not become floating pins, since input impedance at these pins is very high. if any of these pins are left undefined, they may cause unwanted oscillation or intermittent excessive current drain. as these devices are built with cmos technology, normal operating and storage temperature limits, esd and latchup handling precautions pertaining to cmos device handling should be observed.
ald1726e advanced linear devices 7 of 13 typical performance characteristics input bias current as a function of ambient temperature ambient temperature ( c) 100 10 1.0 0.01 0.1 input bias current (pa) 100 -25 0 75 125 50 25 -50 1000 v s = 2.5v open loop voltage gain as a function of frequency frequency (hz) 1 10 100 1k 10k 1m 10m 100k 120 100 80 60 40 20 0 -20 open loop voltage gain (db) v s = 2.5v t a = 25 c 90 0 45 180 135 phase shift in degrees adjustment in input offset voltage as a function of change in ve1 and ve2 change in input offset voltage ? v os (mv) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 -10 -8 -6 -4 -2 0 2 4 6 8 10 ve2 ve1 change in ve1 and ve2 (v) open loop voltage gain as a function of supply voltage and temperature supply voltage (v) 1000 100 10 1 open loop voltage gain (v/mv) 0 2 4 6 8 -55 c t a +125 c r l = 100k output voltage swing as a function of supply voltage supply voltage (v) 0 1 2 3 4 7 6 5 6 5 4 3 2 1 output voltage swing (v) -55 c t a +125 c r l = 100k supply current as a function of supply voltage supply voltage (v) 100 80 40 60 0 20 supply current ( a) 0 1 2 3 4 5 6 t a = -55 c +25 c +70 c +125 c inputs grounded output unloaded -25 c
ald1726e advanced linear devices 8 of 13 common mode input voltage range as a function of supply voltage supply voltage (v) common mode input voltage range (v) 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 t a = 25 c -2500 -2000 -1500 -1000 -500 0 500 1000 1500 2000 2500 total input offset voltage ( v) 100 80 60 40 20 0 distribution of total input offset voltage before and after epad programming example b: v ost after epad programming v ost target = -750 v example a: v ost after epad programming v ost target = 0.0 v v ost before epad programming percentage of units (%) open loop voltage gain as afunction of load resistance 10m load resistance ( ) 10k 100k 1m 1000 100 10 1 open loop voltage gain (v/mv) v s = 2.5v t a = 25 c large - signal transient response v s = 1.0v t a = 25 c r l = 100k c l = 25pf 2v/div 500mv/div 10 s/div large - signal transient response 2v/div 10 s/div 5v/div v s = 2.5v t a = 25 c r l = 100k c l = 25pf small - signal transient response 100mv/div 50mv/div 10 s/div v s = 2.5v t a = 25 c r l = 100k c l = 25pf typical performance characteristics (cont'd)
ald1726e advanced linear devices 9 of 13 0 1 2 3 4 5 6 789 10 500 400 300 200 100 0 equivalent input offset voltage due to change in supply voltage ( v) two examples of equivalent input offset voltage due to change in supply voltage vs. supply voltage supply voltage (v) psrr = 80 db example b: v os epad programmed at v supply = +8v example a: v os epad programmed at v supply = +5v -5 -4 -3 -2 -1 0 1 2345 common mode voltage (v) 500 400 300 200 100 0 equivalent input offset voltage due to change in common mode voltage ( v) example a: v os epad programmed at v in = 0v example b: v os epad programmed at v in = -4.3v example c: v os epad programmed at v in = +5v v supply = 5v cmrr = 80db three examples of equivalent input offset voltage due to change in common mode voltage vs. common mode voltage -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 common mode voltage (v) 50 40 30 20 10 0 equivalent input offset voltage due to change in common mode voltage ( v) v os epad programmed at common mode voltage of 0.25v cmrr = 80db example of minimizing equivalent input offset voltage for a common mode voltage range of 0.5v common mode voltage range of 0.5v typical performance characteristics (cont'd)
ald1726e advanced linear devices 10 of 13 application specific / in-system programming examples of applications where accumulated total input offset voltage from various contributing sources is minimized under different sets of user-specified operating conditions total input v os after epad programming + device input v os psrr equivalent v os cmrr equivalent v os t a equivalent v os noise equivalent v os external error equivalent v os x example a total input offset voltage ( v) 2500 2000 1500 1000 500 0 -500 -1000 -1500 -2000 -2500 v os budget before epad programming v os budget after epad programming + x example b total input offset voltage ( v) 2500 2000 1500 1000 500 0 -500 -1000 -1500 -2000 -2500 + x v os budget before epad programming v os budget after epad programming example c total input offset voltage ( v) 2500 2000 1500 1000 500 0 -500 -1000 -1500 -2000 -2500 + x v os budget before epad programming v os budget after epad programming example d total input offset voltage ( v) 2500 2000 1500 1000 500 0 -500 -1000 -1500 -2000 -2500 + x v os budget after epad programming v os budget before epad programming typical performance characteristics (cont'd)
ald1726e advanced linear devices 11 of 13 8 pin plastic soic package millimeters inches min max min max dim a a 1 b c d-8 e e h l s 1.75 0.25 0.45 0.25 5.00 4.05 6.30 0.937 8 0.50 0.053 0.004 0.014 0.007 0.185 0.140 0.224 0.024 0 0.010 0.069 0.010 0.018 0.010 0.196 0.160 0.248 0.037 8 0.020 1.27 bsc 0.050 bsc 1.35 0.10 0.35 0.18 4.69 3.50 5.70 0.60 0 0.25 soic-8 package drawing l c h s (45 ) e a a 1 b d s (45 ) e
ald1726e advanced linear devices 12 of 13 8 pin plastic dip package millimeters inches min max min max dim a a 1 a 2 b b 1 c d-8 e e 1 e e 1 l s-8 3.81 0.38 1.27 0.89 0.38 0.20 9.40 5.59 7.62 2.29 7.37 2.79 1.02 0 5.08 1.27 2.03 1.65 0.51 0.30 11.68 7.11 8.26 2.79 7.87 3.81 2.03 15 0.105 0.015 0.050 0.035 0.015 0.008 0.370 0.220 0.300 0.090 0.290 0.110 0.040 0 0.200 0.050 0.080 0.065 0.020 0.012 0.460 0.280 0.325 0.110 0.310 0.150 0.080 15 pdip-8 package drawing b 1 s b e e 1 d e a 2 a 1 a l c e 1
ald1726e advanced linear devices 13 of 13 8 pin cerdip package cerdip-8 package drawing a a 1 b b 1 c d-8 e e 1 e e 1 l l 1 l 2 s 3.55 1.27 0.97 0.36 0.20 -- 5.59 7.73 3.81 3.18 0.38 -- 0 5.08 2.16 1.65 0.58 0.38 10.29 7.87 8.26 5.08 -- 1.78 2.49 15 millimeters inches min max min max dim 0.140 0.050 0.038 0.014 0.008 -- 0.220 0.290 0.150 0.125 0.015 -- 0 0.200 0.085 0.065 0.023 0.015 0.405 0.310 0.325 0.200 -- 0.070 0.098 15 2.54 bsc 7.62 bsc 0.100 bsc 0.300 bsc e e 1 c e 1 s b l d b 1 e a l 2 a 1 l 1

▲Up To Search▲

Price & Availability of ALD1726ESAL

	To Download ALD1726ESAL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .